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Physical Design Engineer (Multiple Openings)

Samsung Electronics

Samsung Electronics

Austin, TX, USA
Posted on Thursday, July 4, 2024

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

  • Work as part of CPU IP, working on significant deliverables for the team. Tasked with driving synthesis, block and full chip implementation through sign-off with the latest industry P&R/STA flows and tools. Responsible from synthesis to place and route of a GPU block through signoff flows including timing and physical verification. Synthesis, Floor plan, Place & Route in chip-level and hierarchical physical implementation environment. Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable. Interact with RTL counterpart to resolve design issues pertaining to block closure and Optimize GPU block to meet aggressive power/performance/area targets.

Skills and Qualifications

  • Master’s degree in Electrical Engineering, Electronics Engineering, Bioengineering, or a related field.
  • Requires completion of a graduate-level course, research project, or internship involving the following:
    1. Verilog/SystemVerilog/VHDL;
    2. Physical design flow including gate level netlist, floor planning, partitioning, power planning, placement, synthesis, and/or routing;
    3. RTL design;
    4. Synthesis and Timing analysis;
    5. UVM/OVM/VMM;
    6. Test bench development; and
    7. Design closure (DRC/LVS).

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