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Senior Hardware Design Engineer

Marvell

Marvell

Software Engineering, Other Engineering, Design
Santa Clara, CA, USA
Posted on Thursday, July 11, 2024

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Hardware Design Senior Staff Engineer with Marvell, you’ll be a member of the Central Engineering group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You’ll be part of the printed circuit board (PCB) engineering team designing boards for many different groups at Marvell. Additionally, Marvell is designing more complex chips and boards than our competitors, for higher speeds than anyone else. We’re on the leading edge of this technology and you’ll love being a part of this.

What You Can Expect

  • Responsible for board development for CE test platforms to support high speed ComPhy test infrastructure.
  • Perform board level circuit design for power and clock distribution and logic design for evaluation test systems.
  • Create board design specs, capture circuit schematics, and layout guidelines.
  • perform bench level testing and debug on test boards and measurement of noise/jitter, eye patterns and S-parameters.
  • work and collaborate with cross-functional teams in resolving complex issues.

What We're Looking For

  • Minimum BSEE degree in Electrical Engineering, 3 or more-year experience in data communication and hardware development
  • Proficiency in ORCad Capture, Cadence Allegro, and Python, FPGA/CPLD programming
  • Hands on Experience in lab test equipment (Oscilloscopes, VNA, BERT etc.) and standard lab operating procedures.
  • Knowledge circuit design for power supply, clock distribution and in basic communication protocols, such as USB, I2C, MDC/MDIO, SPI, JTAG.
  • Ability to communicate well and work across internal and external engineering groups in resolving complex issues.

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Expected Base Pay Range (USD)

121,840 - 182,500, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.

This role is eligible for our hybrid work model in which you will be able to split time between working from home and on-site in a Marvell office.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.