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Silicon Packaging Design Engineer

Intel

Intel

Design
Phoenix, AZ, USA
USD 104,890-148,080 / year + Equity
Posted on May 10, 2025

Job Details:

Job Description:

As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO. Foundry Services will be a world-class foundry business and major provider of US and European based capacity to serve customers globally.

Foundry Services will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IPs. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages.

This business unit is completely dedicated to the success of its customers with full PandL responsibilities. This model will ensure that our foundry customers' products receive our utmost focus in terms of service, technology enablement, and capacity commitments. FS is already engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications.

Silicon Packaging Design Engineer job responsibilities include but not limited to:

  • Drives end-to-end development for substrate design from concept through tapeout and implements physical layout and routing of the package design.
  • Follows substrate design rules, conducts routing studies to establish design, performance, and cost tradeoffs.
  • Works closely with silicon and hardware teams to optimize silicon/package/board performance and pinout.
  • Defines substrate design rules, conducts internal and external reviews, and resolves DRCs to optimize package design.
  • Completes documentation and collateral into the system of record tool.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.

Minimum Qualifications:

  • US Citizenship required.
  • Ability to obtain a US Government Security Clearance.
  • Bachelor's degree in Electrical / Mechanical Engineering, or in a STEM related field of study.
  • 3+ months experience with microelectronic package or PCB physical layout design using package design tools such as Siemens Xpedition, Cadence Allegro, or CAD.

Preferred Qualifications:

  • Active US Government Security Clearance with a minimal of a Secret Level.
  • Master's degree in in Electrical / Mechanical Engineering, or in a STEM related field of study.
  • Performing package I/O routing starting day one.
  • Strong analytical ability and problem-solving skills: identifying, isolating, and debugging issues and providing creative solutions.
  • Microelectronic package substrate technology development.
  • Package design tools such as Package Layout Automation (PLA) and FIELD.
  • Microelectronic package electrical modeling and simulation tools such as PowerDC, HyperLynx, Q3D, and HFSS.
  • Extract signal integrity and/or power delivery electrical models and run AC/DC/Frequency Domain simulations.
  • Scripting using Python, VB, C, and or other languages.

Job Type:

College Grad

Shift:

Shift 1 (United States of America)

Primary Location:

US, Arizona, Phoenix

Additional Locations:

Business group:

Intel Foundry is dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. As stewards of Moore's Law, we innovate and foster collaboration within an extensive partner ecosystem to advance technologies and enable our customers to design leadership products. Our strategic investments in geographically diverse manufacturing capacities bolster the resilience of the semiconductor supply chain. Leveraging our technological prowess, expansive manufacturing scale, and a more sustainable supply chain, Intel Foundry empowers the world to deliver essential computing, server, mobile, networking, and automotive systems for the AI era. This position is part of the Foundry Services business unit within Intel Foundry, a customer-oriented service organization that is dedicated to the success of its customers with full P&L responsibilities. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$104,890.00-$148,080.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.