Hardware Power Test Engineering Manager, Platforms
Hardware Power Test Engineering Manager, Platforms
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Minimum qualifications:
- Master's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
- 6 years of experience working in DC-DC power design or testing, or 5 years of experience with an advanced degree.
- 3 years of experience in engineering management.
- Experience in one or more of the following: DC-DC converters, open compute power architecture, SoC power architecture, and component-/tray-/rack-level power management.
Preferred qualifications:
- Experience in power measurement equipment such as oscilloscopes, programmable power supplies, spectrum analyzers, DMMs and function generators.
- Experience in one or more scripting languages (e.g., Python) for test automation, data collection, and analysis.
- Knowledge of power testing methodologies and of bench level hardware validation using test equipment.
About the job
As a Hardware Power Test Engineering Manager, you will manage a team of hardware test engineers to participate in hardware design reviews and perform onboard power validation. You will also be responsible for liaison between hardware engineering teams and the lab team to ensure lab resources are accounted for, and to ensure the team is ready for new products entering the labs or sustaining efforts.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
- Define, execute, and document electrical characterization, validation, and qualification of on-board system-level power distribution network (PDN), covering from the DC-DC power converter design to ASIC power integrity validation.
- Drive improvement on power measurement methodologies, test automation, and processes across compute and Machine Learning products.
- Support design engineers with debug, component validation, and failure analysis of released products.
- Collect and analyze aggregated data to enable data driven engineering decisions, report on findings, reduce test data, and investigate test outcomes to a hardware interface or component level.
- Work with hardware designers and other diagnostics development teams to understand new project' power distribution architectures and system test requirements to develop resource requirements.
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