Design Verification Engineer, Multimedia
Design Verification Engineer, Multimedia
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog.
- Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for ASICs.
- Experience with object oriented programming.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with Formal verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
- Experience with performance verification of Application-specific integrated circuits (ASICs), ASIC components, or ASIC standard interfaces and memory system architecture.
- Experience in verification of multimedia IPs (Camera/Display/Video Codec) or Machine Learning IPs.
- Experience with Google Line System (GLS), low-power DV, and support of SOC DV.
About the job
Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Responsibilities
- Plan the verification of complex Multimedia HW IPs at Subsystem and full chip level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and UVM.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.
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