DDR Design Engineer
Apple
Summary
Description
Minimum Qualifications
- BS degree in technical discipline with minimum 3 years of relevant experience.
Key Qualifications
Preferred Qualifications
- RTL design using Verilog or SystemVerilog, assertion writing
- Design of state machines, data paths, arbitration and clock domain crossing logic
- Logic synthesis, timing constraints
- Exposure to Design For Test, understanding of scan concept and writing DFT friendly RTL
- Unified Power Format for simulation, synthesis and electrical rule checking Equivalence checking
- Prior experience in DDR PHY design and mixed-signal environment is a plus
Education & Experience
Additional Requirements
Pay & Benefits
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