RFIC - PLL Design Engineer
Apple
Summary
Description
Minimum Qualifications
- BS and 3 + years of relevant industry experience.
- Experience with RF/analog and mixed-signal design experience in groundbreaking RF CMOS design.
- Experienced in the design and development of fractional N Synthesizers, Digital PLLs, Analog PLLs, and LO-Gen for high-performance applications and also low power applications.
- Hands-on experience designing TDC, GRO, Digital Filters, Sigma Delta Modulators, Pre-scalers, MMD, DCOs, PFD-CP, and VCOs. Modeling, analysis, and design of SD noise cancellation and spur cancellation techniques.
- Skilled in using Cadence Virtuoso, Spectre RF, Matlab, and EM simulation tools (e.g., EMX, HFSS).
- Familiarity with mixed-signal verification methodologies (SystemVerilog, AMS, Nanotime).
Key Qualifications
Preferred Qualifications
- Direct experience in designing and bringing wireless transceivers into mass production in deep sub-micron RFCMOS technology.
- Extensive knowledge in fractional N synthesizer and LOGen silicon characterization and debugging.
- Deep understanding of analog, mixed-signal, and RF circuit design. This includes LNAs, PAs, mixers, baseband filters, VGAs, and calibration methods associated with high-performance wireless systems.
- Familiarity with various RF transceiver architectures and their trade-offs and system specifications, and ability to work with system architects to translate system requirements into circuit requirements at the IC level.
- MSEE and/or PhD with extensive experience.
Education & Experience
Additional Requirements
Pay & Benefits
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