SoC Physical Design Verification Engineer
Apple
Summary
Description
Minimum Qualifications
- Minimum BS in Electrical/Electronics/Computer Engineering or related field.
- 3+ years of relevant industry experience.
- Strong knowledge of physical verification flows and methodology.
- Knowledge of all aspects of ASIC physical design.
- Scripting skills to debug flow related issues and make enhancements as appropriate.
- Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
- Strong understanding of place and route design blocks flow and methodology.
- Real chip tapeout experience with a track record of successful signoff.
Key Qualifications
Preferred Qualifications
- MS in Electrical/Electronics/Computer Engineering or related field.
- Proficient scripting skills and automation experience.
- Layout or floorplan design experience.
- Physical design verification and debug experience including mixed signal and digital IP integrations at block and full-chip hierarchies.
Education & Experience
Additional Requirements
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