Low Power RTL Design Engineer
Apple
Summary
Description
Minimum Qualifications
- BS and 3+ years of relevant experience.
- Proved track record in power / clock / reset management logic design.
- Proficiency in Verilog language.
- Power management logic verification and debug experience.
- Understand ASIC low power design techniques
- Knowledge of CDC, RDC, STA and UPF.
- Experience with Power tools, e.g. PTPX and Power Artist.
- Proficiency in scripting languages (Shell, Perl or Python).
- Basic knowledge on common SOC components, e.g. CPU, fabric, peripherals and PCIe.
- Strong problem solving and analytical skills.
Key Qualifications
Preferred Qualifications
- SoC level power management logic experience.
- SOC top level integration experience.
- System architecture knowledge.
- In depth knowledge of common SOC components, e.g. CPU, fabric, peripherals and PCIe.
- Post-silicon functional debug and power correlation experience.
Education & Experience
Additional Requirements
Pay & Benefits
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