RFIC Design Engineer
Apple
Design
San Diego, CA, USA
Posted 6+ months ago
Summary
Posted:
Role Number:200575181
Do you have a passion for invention and self-challenge. Do you thrive with pushing the limits of what’s considered feasible? As part of an outstanding team, you’ll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You’ll work across fields to transform improved hardware elements into a coordinated design. Join us, and you’ll help us innovate new technologies that continually outperform the previous iterations! By collaborating with other product development groups across Apple, you’ll push the industry boundaries of what wireless systems can do and improve the product experience for our customers worldwide. The wireless RFIC team architects, designs, and validates radio transceivers integrated into sophisticated wireless SoCs. Our wireless organization is responsible for all aspects of wireless silicon development that transform the user experience at the product level, all of which is driven by an outstanding vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering! As an engineer within the Wireless Radio team, you will be at the center of a wireless SoC design group, chipping in to Apple’s innovative wireless connectivity solutions into hundreds of millions of products.
Description
As an RFIC Design Engineer, you will be responsible for providing RFIC solutions for wireless SoC and driving them to mass production for Apple’s Wireless Connectivity products. Responsibilities include: - Led design of radio transceiver chains, including TX, RX, and PLL-LOGen for wireless connectivity products. - Drive radio KPI (power, area, performance) to meet product requirements. - Work with multi-functional teams including platform architecture, wireless design, RF HW and SW to define radio features enabling wireless innovation. - Work closely with RF Systems in block level and high level specifications of the TX and RX line ups and PLL-LOGen, and accurate distribution of spec margins in the chain. - Hands-on design contributions, starting from concept, architecture, and topology to transistor-level feasibility studies and KPI trade-off analysis to actual design, simulations, and extractions. - Design of RF and Analog loopbacks for calibration and compensation. - Work through Co-Existence scenarios and design to meet the CoEx requirements. - Be responsible for the floorplan layout and verification of the design to ensure a successful tape-out. - Close collaboration with RFIC test engineers in the bring up, debug and optimization of the wireless connectivity chip through the productization. - Provide design versus silicon measurements correlation and compliance with specifications for volume production.
Minimum Qualifications
- BS and 10+ years of relevant industry experience.
- Shown RF/analog and mixed-signal design experience in groundbreaking RF CMOS design.
- Strong understanding of analog design concepts such as analysis of noise, linearity, mismatch, stability, and other analog impairments.
- Experience in Cadence Virtuoso, Spectre RF, Matlab, EM simulation (EMX, HFSS), and similar tools.
- Direct experience in designing and bringing wireless transceivers into mass production in deep sub-micron RFCMOS technology.
- Experience should also include understanding DFT and DFM techniques for mass production environments.
Key Qualifications
Preferred Qualifications
- MSEE and PhD plus relevant industry experience.
- Solid Understanding of the impact of modulation type on radio architecture and requirements.
- Validated capability to work with digital design group for an optimum partition between digital and analog domains.
- Familiarity with the integration flows and challenges of wireless SoCs.
- Good understanding of desense and can work with board RF/HW/Antenna teams to optimize board/module layouts for desense mitigation.
- Familiarity with mixed-signal mode verification methodology (SystemVerilog, AMS, Nanotime).
- Extensive experience in Silicon characterization and debugging.
- Ability to drive strong production test/QA methodologies.
Education & Experience
Additional Requirements
Pay & Benefits
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