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ASIC Design Engineer - Fabric/Interconnect



Santa Clara, CA, USA
Posted on Friday, May 24, 2024


Role Number:200552561
Imagine what you could do here. At Apple, phenomenal ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Apple is owning the charge in dedication mobile computing with innovative SOC's announced with each of its revolutionary new product offerings. At the core of all Apple mobile SOC's, is an on-chip system interconnect bus that supplies the SOC agents with their requested load and store data from on chip and off chip memories. With every generation the max bandwidth, the lowest latency, the lowest area, and lowest power requirements are more exacting and require sophisticated planning in order to achieve on Apple's schedules! Be part of the team creating the architecture and design for the on-chip system interconnect bus for next generation Apple SOC's!


As a member of the SoC Design team, you will be responsible for the following: - Analyze architectural requirements of next generation of on-chip fabric and define scalable interconnect components - Coding high-quality RTL, with embedded assertions and cover points. - Writing detailed micro-architectural specifications. - Work with multi-functional team to define and implement logic IP. - Collaborating with multi-functional teams to explore solutions to improve performance while minimizing power and area. - Working closely with design verification and formal verification teams to debug and verify functionality and performance.

Minimum Qualifications

Key Qualifications

  • Extensive experience in front-end ASIC RTL digital logic design using Verilog or System Verilog
  • Tight-knit collaboration skills with excellent written and verbal communication skills.
  • Familiar with multiple power domains, multiple clock domains and asynchronous interfaces.
  • Strong understanding of flow control, arbitration, on-chip interconnects, QoS, topology, and performance analysis
  • Experience implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, logic equivalence checks.
  • Power and clock management designs desirable
  • Familiarity on flow automation scripts using Perl, Python, Makefile and shell scripts
  • Experience in ASIC IP development using extensive flow automation a plus

Preferred Qualifications

Education & Experience

Bachelors degree + 3 years of industry experience is required.

Additional Requirements

Pay & Benefits

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.