ASIC Design Engineer - Fabric/Interconnect
Apple
Summary
Description
Minimum Qualifications
Key Qualifications
- Extensive experience in front-end ASIC RTL digital logic design using Verilog or System Verilog
- Tight-knit collaboration skills with excellent written and verbal communication skills.
- Familiar with multiple power domains, multiple clock domains and asynchronous interfaces.
- Strong understanding of flow control, arbitration, on-chip interconnects, QoS, topology, and performance analysis
- Experience implementation tasks such as synthesis, timing, area/power analysis, linting, CDC/RDC, logic equivalence checks.
- Power and clock management designs desirable
- Familiarity on flow automation scripts using Perl, Python, Makefile and shell scripts
- Experience in ASIC IP development using extensive flow automation a plus
Preferred Qualifications
Education & Experience
Additional Requirements
Pay & Benefits
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