ASIC Design Engineer - Memory Cache Controller
Apple
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Description
Minimum Qualifications
Key Qualifications
- Development of memory systems.
- Experience in RTL/micro-architecture definition.
- Experience in PPA (performance/power/area) analysis.
- Knowledge of dedication coherent memory system or interconnect architectures.
- Strong cache design background including good understanding of different memory organizations and tradeoffs.
- Knowledge of dedication memory subsystem and dram controller.
- Hands on Experience with multi-processor cache coherence protocols
Preferred Qualifications
Education & Experience
Additional Requirements
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This job is no longer accepting applications
See open jobs at Apple.See open jobs similar to "ASIC Design Engineer - Memory Cache Controller" Ellis H-1B.