Standard Cell Design Methodology & Flow Engineer
Apple
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Description
Minimum Qualifications
Key Qualifications
- Flow automation skills in standard cells development and integration to improve execution efficiency.
- Knowledge of Verilog/SystemVerilog, UDPs, Verilog simulation and formal verification
- Exposure to Design For Test, scan concept and write DFT friendly RTL
- Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation.
- Proficiency of using Python/Perl/TCL
- 5+ years’ experience in the VLSI industry
- Great interpersonal skills to champion initiatives internally and externally, and for effective communication with executive management and external partners.
- Experience with various EDA tools for synthesis, place-route, Liberty format is a bonus
- Understands all aspects of implementation specification, design, timing, power, and flow automation
- Familiar with foundry ecosystem and benchmarking practice is desirable but not required
Preferred Qualifications
Education & Experience
Additional Requirements
Pay & Benefits
Apple is an equal opportunity employer that is committed to inclusion and diversity. We take affirmative action to ensure equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.
This job is no longer accepting applications
See open jobs at Apple.See open jobs similar to "Standard Cell Design Methodology & Flow Engineer" Ellis H-1B.