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SENIOR MANAGER SILICON DESIGN ENGINEER

THE ROLE:

As a member of the Strategic Silicon Solutions Group Physical design team, you will help bring to life cutting-edge designs. As a member and lead of the Backend Full Chip Timing team, you will work closely with the PD architects, design leads, IP teams, Physical Design leads and PD/STA engineers to achieve first-pass silicon success. You will be expected to lead design closure activities in the backend from a timing closure perspective. The role will require a deep understanding of timing constraints development as well as FCT timing signoff.

THE PERSON:

This person will work closely with Fellows, Principal Engineers, Architects, collaborate with cross functional worldwide teams across Physical Design, Timing Analysis, Synthesis, Physical Verification, Power signoff, and mentor/coach/guide Design Engineers. The candidate should be highly accurate and detail-oriented, possessing good communication and problem-solving skills.

KEY RESPONSIBLITIES:

• Lead the full chip timing team for constraints and timing signoff.
• Own end-to-end delivery of designs (SOC and Sub-system integration) from timing constraints and timing signoff perspective.
• Work closely with the SOC Architecture team for SOC clocks & STA for statistical timing target goals.
• Understanding clock design requirements and making sure they are correctly set up in SDC.
• Understand timing margins (LVF/SSTA/Variations etc.) on the latest tech nodes and work with timing methodology teams for future and current projects.
• Understand design requirements, timelines and various milestones of a project and deliver FCT closure accordingly.
• Lead the timing ECO phase and plan for on-time project tape out.
• Collaborate with CAD and EDA vendors to further strengthen AMD timing closure and constraints methodology.

PREFERRED EXPERIENCE:

• Experienced PD professional with 18+ years of industry experience in STA, constraints, timing signoff and physical design
• Expert user of industry-standard PD tools like SNPS PT/GCA (must) and ICC2/FC (desired).
• Good experience and understanding of DFT timing concepts, MBIST, Top level clock -implementation, Place and Route flows -floorplanning and placement, CTS and Route.
• Good experience with Perl/TCL/Shell/Python scripting, and Verilog RTL design.
• Excellent presentation and inter-communication skills.

ACADEMIC CREDENTIALS:

• • Bachelors or Master’s degree in Computer/Electronics/Electrical Engineering

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.